1. Field of the Invention
The present invention relates generally to an ATM (Asynchronous Transfer Mode) cell synchronization circuit. More specifically, the invention relates to an ATM cell synchronization circuit which establishes synchronization of an ATM cell by detecting fifth order byte as an HEC (Header Error Control) byte among a cell header of an ATM cell string consisted of fifty-three bytes per one cell and transmitted with parallel development into eight strings.
2. Description of the Related Art
An ATM cell in an ATM communication system is consisted of fifty-three bytes per one cell, having a cell format shown in FIG. 12. In the ATM cell, the leading five byte is a region referred to as a header, and the remaining forty-eight bytes is a so-called payload region. Among five bytes in the header, an information contained in fifth order byte is a portion referred to as HEC (Header Error Control) byte.
In a cell string which is a flow of the cells, in which the ATM cells are continuous, it is required to detect the position of each cell. This is referred to as cell synchronization. In order to perform cell synchronization, the HEC byte region is provided.
In an ATM cell signal output device or the like to a transmission path, information in the first to fourth order bytes are arithmetically processed according to a predetermined rule to store the result of the arithmetic operation in the HEC byte region.
An ATM cell synchronization circuit for foregoing cell synchronization is provided in a receiver device or the like for receiving an ATM cell signal. Per every four bytes of the input ATM cell string, the foregoing arithmetic operation is performed with shifting per one byte to check whether the result of the arithmetic operation matches with the content of the fifth order byte to detect the position of the HEC byte and thus detect a positional relationship of the cells, namely cell synchronization.
In the conventional ATM cell synchronization circuit, process has been performed using the ATM cell signal developed into eight parallel strings (eight bits parallel strings, namely per one byte). It should be appreciated that performing process for the data signal of the ATM cell string developed into eight parallel strings may not cause any problem when a transmission speed is low, whereas, it becomes impossible to adapted for high speed operation due to limitation of speed of operations of components of the ATM cell synchronization circuit.
In order to adapt for high transmission speed, there has been proposed a technology for slow-down the nominal speed of the process by further parallel development. However, since the ATM cell is consisted of fifty-three bytes (fifty-three is prime factor) per one cell as set forth above, it is difficult to construct digital circuit for parallel development into a strings of 1/53.
Accordingly, as disclosed in Japanese Unexamined Patent Publication (Kokai) No. Heisei 4-247744, for the ATM cell consisted of fifty-three bytes, one or more dummy bytes are inserted in the cell to make the cells to be consisted of fifty-four byte or sixty byte to facilitate parallel development.
In the technology disclosed in Japanese Unexamined Patent Publication No. Heisei 4-247744, it is necessary to insert the dummy data in the cell. Therefore, it has been necessary to convert the processing speed for the amount of the inserted dummy data or to share a cell band for the dummy data in order to perform the same process at the same speed.